A Novel Two-Split Capacitor Array with Linearity Analysis for High-Resolution SAR ADCs
نویسندگان
چکیده
A novel two-split capacitor (T-SC) array structure for Successive Approximation Register (SAR) analog-to-digital converter (ADC) is proposed. When used as digital –to-analog converter (DAC), this circuit reduced the chip area by 27.7% in comparing with the conventional Split Capacitor (SC) at resolution=14. The area reduction effect can be more significant with the increasing resolution of ADC. The capacitor mismatch and parasitic effects of this proposed structure are analyzed in theory. Behavioral simulations were performed to demonstrate the effectiveness of this proposed structure. This simulation was only performed for capacitor mismatch. Simulation results show that T-SC array could achieve good binary-weighted performance and the standard deviation of its DNL was 0.51LSB when the standard deviation of capacitor was 0.025%. Furthermore, the analysis in this paper is provided for designers to make a tradeoff among resolution, CMOS process, circuit structure and capacitor size in their design of SAR ADC.
منابع مشابه
Implementation of High Speed Low Power Split-SAR ADCS Using Vcm and Capacitor Based Switching
This paper analyzes the parasitic effects in SAR ADCs. Successive approximation technique in ADC is well known logic, where in the presented design the linearity analysis of a Successive Approximation Registers (SAR) Analog-to-Digital Converter (ADC) with split DAC structure based on two switching methods: VCM -based switching, Switch to switchback process. The main motivation is to implement d...
متن کاملImplementation of High Speed Low Power Split-SAR ADCs
This paper analyzes the parasitic effects in SAR ADCs. Which achieves a significant switching energy saving when compared with set-and-down and charge-recycling switching approaches. Successive approximation technique in ADC is well known logic, where in the presented design the linearity analysis of a Successive Approximation Registers (SAR) Analog-to-Digital Converter (ADC) with split DAC str...
متن کاملVariable resolution SAR ADC architecture with 99.6% reduction in switching energy over conventional scheme
A novel energy-efficient switching method for variable resolution successive approximation register (SAR) analogue-to-digital converters (ADCs) is presented. The proposed switching scheme achieves switching energy inspired by the early reset merged capacitor switching algorithm (EMCS) and monotonic capacitor switching procedure. Besides, the dummy capacitors are used to further reduce power con...
متن کاملLinearity analysis of single-ended SAR ADC with split capacitive DAC
This paper proposes the design of a 6-bit single-ended SAR ADC with a variable sampling rate at a maximum achievable speed of 50 MS/s. The SAR ADC utilizes the split capacitor array DAC with a non-conventional split-capacitor value. The influence of switches in the capacitive DAC on the ADC’s non-linearity is analysed. According to the fulfilled analysis the recommendations for switches and cap...
متن کاملMismatch-Immune Successive- Approximation Techniques for Nanometer CMOS ADCs
During the past decade, SAR ADCs have enjoyed increasing prominence due to their inherently scaling-friendly architecture. Several recent SAR ADC innovations focus on decreasing power consumption, mitigating thermal noise, and improving bandwidth, however most of those using non-hybrid architectures are limited to moderate (8-10 bit) resolution. Assuming a nearly rail-to-rail dynamic range, com...
متن کامل